A variety of deposition techniques are used in the fabrication of integrated circuits, including physical vapor deposition (PVD), chemical vapor deposition (CVD) and, more recently, atomic layer deposition (ALD).
In ALD, reactants are supplied to the workpiece in alternating pulses in a cycle. Preferably, each cycle forms no more than about one monolayer of lining material by adsorption and preferably by chemisorption. The substrate temperature is kept within a window facilitating chemisorption. In particular, the substrate temperature is maintained at a temperature low enough to maintain intact bonds between adsorbed species and the underlying surface, and to prevent decomposition of the reactant species. On the other hand, the substrate temperature is maintained at a high enough level to avoid condensation of reactants and to provide the activation energy for the desired surface reactions in each phase. Of course, the appropriate temperature window for any given ALD reaction will depend upon the surface termination and reactant species involved.
Each pulse or phase of each cycle is preferably self-limiting in effect. In the examples set forth below, each of the phases are self-terminating (i.e., an adsorbed and preferably chemisorbed monolayer is left with a surface non-reactive with the chemistry of that phase). An excess of reactant precursors is supplied in each phase to saturate the structure surfaces. Surface saturation ensures reactant occupation of all available reactive sites (subject to physical size restraints, as discussed in more detail below), while self-termination prevents excess film growth at locations subject to longer exposure to the reactants. Together, saturation and self-terminating chemistries ensure excellent step coverage.
As will be understood from the above, ALD affords much greater conformality than PVD or CVD processes. However, less than perfect conformality is sometimes desirable. For example, U.S. Pat. No. 6,482,733 describes a damascene metallization process in which a non-conformal process, such as PVD or CVD, is first conducted to seal pores in the trench and via sidewalls of a porous, low k insulating layer. A subsequent ALD process conformally lines the trench and via walls without depositing conductive material deep into the pores of the insulating material. CVD and PVD, however, provide limited control over the conformality of the deposition.
U.S. Pat. No. 6,759,325 (“'325 patent”), the disclosure of which is incorporated herein by reference, describes a process in which the conformality of the deposition can be more finely controlled. The '325 patent describes methods allowing tailored conformality, ranging from the near perfect conformality of ALD to the level of conformality afforded by chemical vapor deposition (CVD). In particular, the methods include an alternating deposition process, whereby a plurality of sequential reactant pulses are separated from one another. This alternating process is optimized to achieve a level of conformality between that of atomic layer deposition (ALD) and chemical vapor deposition. A sequence is provided of at least two different, mutually reactive reactants in temporally separated and alternating reactant pulses. Separations of the reactant pulses and durations of the reactant pulses are selected to control the conformality of the film deposited in the openings in the surface of the semiconductor substrate, wherein the separations and durations are selected to achieve reduced conformality compared to a corresponding atomic layer deposition (ALD) process that is optimized to achieve maximum conformality with minimum cycle length for the substrate topography. The semiconductor substrate is exposed to the sequence of the reactant pulses with the selected separations and durations to deposit the film.